View IR3500VMPBF_8924919.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ir3500v page 1 of 34 july 28, 2008 data sheet xphase3 tm vr11.1 cpu vtt control ic description the ir3500v control ic combined with one or more xphase3 tm phase ic implement the control and mosfet driver functions for a vr11.1 cpu vtt power supply. features 1 to x phase operation with matching phase ic 0.7% overall system set point accuracy programmable 250khz to 9mhz daisy-chain digital ph ase timing clock oscillator frequency provides a pe r phase switching frequency of 250khz to 1.5mhz witho ut external components programmable dynamic vid slew rate programmable load line output impedance high speed error amplifier with wide bandwidth of 30mhz and fast slew rate of 12v/us programmable converter current limit during soft s tart, hiccup with delay during normal operation central over voltage detection with programmable t hreshold and communication to phase ic(s) over voltage signal output to system with overvolt age detection during powerup and normal operation detection and protection of open remote sense line and open control loop ic bias linear regulator control with programmable output voltage and uvlo programmable vrhot function monitors temperature o f power stage through a ntc thermistor remote sense amplifier with true converter voltage sensing and less than 50ua bias current simplified pgood output provides indication of pro per operation and avoids false triggering small thermally enhanced 32l 5mm x 5mm mlpq packag e rohs compliant csin- 15 vcc 13 eain 16 ishare 1 sw 12 gateh 11 boost 10 csin+ 14 dacin 2 clkin 6 phsin 4 phsout 5 gatel 8 pgnd 7 vccl 9 lgnd 3 ir3505 ccs l cbst2 rcs cvccl cin vout+ vout sense- vout sense+ vout- cout distribution impedance rcp cvdac rvcclfb1 ccp rosc vidsel 32 vid7 1 vid6 2 vid5 3 vid4 4 vid3 5 vid2 6 vccldrv 30 vid1 7 vid0 8 enable 9 vosen- 12 vdac 21 vsetpt 19 vcclfb 29 ocset 20 lgnd 24 phsin 27 phsout 26 clkout 25 eaout 16 fb 15 vosen+ 13 vdrp 17 vrhot 10 hotset 11 ss/del 22 rosc / ovp 23 pgood 31 vo 14 vccl 28 iin 18 ir3500v rvdac rvcclfb2 rfb rhotset2 rhotset1 rdrp 4.7uf cvccl cfb rocset rfb1 ccp1 css/del pgood 12v rvccldrv vid3 vid2 vid4 vrhot enable rfb2 rthermistor1 rthermistor2 close to power stage figure 1 ? single phase vr11.1 cpu vtt application circuit downloaded from: http:///
ir3500v page 2 of 34 july 28, 2008 ordering information device package order quantity ir3500v mtrpbf 32 lead mlpq (5 x 5 mm body) 3000 per reel * ir3500v mpbf *samples only 32 lead mlpq (5 x 5 mm body) 100 piece strips absolute maximum ratings stresses beyond those listed below may cause perman ent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specif ications are not implied. operating junction temperature?????.. 0 o c to 150 o c storage temperature range???????.-65 o c to 150 o c esd rating???????????????hbm class 1c jedec standar d msl rating???????????????2 reflow temperature???????????.260 o c pin # pin name v max v min i source i sink 1-8 vid7-0 7.5v -0.3v 1ma 1ma 9 enable 3.5v -0.3v 1ma 1ma 10 vrhot 7.5v -0.3v 1ma 50ma 11 hotset 7.5v -0.3v 1ma 1ma 12 vosen- 1.0v -0.5v 5ma 1ma 13 vosen+ 7.5v -0.5v 5ma 1ma 14 vo 7.5v -0.3v 5ma 25ma 15 fb 7.5v -0.3v 1ma 1ma 16 eaout 7.5v -0.3v 25ma 10ma 17 vdrp 7.5v -0.3v 35ma 1ma 18 iin 7.5v -0.3v 100ma 1ma 19 vsetpt 3.5v -0.3v 1ma 1ma 20 ocset 7.5v -0.3v 1ma 1ma 21 vdac 3.5v -0.3v 1ma 1ma 22 ss/del 7.5v -0.3v 1ma 1ma 23 rosc/ovp 7.5v -0.3v 1ma 1ma 24 lgnd n/a n/a 20ma 1ma 25 clkout 7.5v -0.3v 100ma 100ma 26 phsout 7.5v -0.3v 10ma 10ma 27 phsin 7.5v -0.3v 1ma 1ma 28 vccl 7.5v -0.3v 1ma 20ma 29 vcclfb 3.5v -0.3v 1ma 1ma 30 vccldrv 10v -0.3v 1ma 50ma 31 pgood vccl + 0.3v -0.3v 1ma 20ma 32 vidsel 7.5v -0.3v 5ma 1ma downloaded from: http:///
ir3500v page 3 of 34 july 28, 2008 recommended operating conditions for reliable opera tion with margin 4.75v v ccl 7.5v, -0.3v vosen- 0.3v, 0 o c t j 100 o c, 7.75k r osc 50.0 k electrical specifications the electrical characteristics involve the spread o f values guaranteed within the recommended operatin g conditions. typical values represent the median val ues, which are related to 25c. c ss/del = 0.1 f +/-10%. parameter test condition min typ max unit vdac reference system set-point accuracy deviation from table 1 p er test circuit in figure 2 -0.7 0.7 % source & sink currents include ocset and vsetpt cur rents 30 44 58 a vr11 vidx input threshold float vidsel 500 600 70 0 mv vr11 vidx input bias current float vidsel. 0v v(vidx) 2.5v. -1 0 1 a vidsel pull-up resistance 3.0 4.0 5.0 k oscillator rosc voltage 0.570 0.595 0.620 v clkout high voltage i(clkout)= -10 ma, measure v(vc cl) ? v(clkout). 1 v clkout low voltage i(clkout)= 10 ma 1 v phsout frequency r osc = 50.0 k 225 250 275 khz phsout frequency r osc = 24.5 k 450 500 550 khz phsout frequency r osc = 7.75 k 1.35 1.50 1.65 mhz phsout high voltage i(phsout)= -1 ma, measure v(vcc l) ? v(phsout) 1 v phsout low voltage i(phsout)= 1 ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % remote sense differential amplifier unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset voltage 1v v(vosen+) - v(vosen-) -3 0 3 mv source current 1v v(vosen+) - v(vosen-) 0.5 1.0 1.7 ma sink current 1v v(vosen+) - v(vosen-) 2 12 18 ma slew rate 1v v(vosen+) - v(vosen-) note1 2 4 8 v/us vosen+ bias current 1 v < v(vosen+) 30 50 ua vosen- bias current -0.3v vosen- 0.3v, all vid codes 30 50 ua vosen+ input voltage range v(vccl)=7v 5.5 v high voltage v(vccl) ? v(vo) 0.5 1 v low voltage v(vccl)=7v 250 mv enable input vr 11 threshold voltage enable rising 830 855 880 mv vr 11 threshold voltage enable falling 780 805 830 mv vr 11 hysteresis 25 50 75 mv bias current 0v v(enable) 3.3v -5 0 5 a blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns downloaded from: http:///
ir3500v page 4 of 34 july 28, 2008 parameter test condition min typ max unit soft start and delay start delay (td1) 1.0 2.9 3.5 ms soft start time (td2) to reach 1.1v 0.8 2.2 3.25 ms vid sample delay (td3) 0.3 1.2 3.0 ms pgood delay (td4 + td5) 0.5 1.2 2.3 ms oc delay time v(iin) ? v(ocset) = 500 mv 75 125 300 us ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.7 1.4 1.9 v charge current 35.0 52.5 70.0 a discharge current 2.5 4.5 6.5 a charge/discharge current ratio 10 12 16 a/ a charge voltage 3.75 v delay comparator threshold relative to charge volta ge, ss/del rising 80 mv delay comparator threshold relative to charge volta ge, ss/del falling 110 mv delay comparator hysteresis 30 mv vid sample delay comparator threshold 3.0 v discharge comp. threshold 150 200 275 mv error amplifier input offset voltage measure v(fb) ? v(vsetpt). no te 2 -1 0 1 mv fb bias current -1 0 1 a vsetpt bias current r osc = 24.5 k 23.00 24.25 25.50 a dc gain note 1 100 110 120 db bandwidth note 1 20 30 40 mhz slew rate note 1 7 12 20 v/ s sink current 0.40 0.85 1.00 ma source current 5 8 12 ma minimum voltage 120 250 mv maximum voltage measure v(vccl) ? v(eaout) 500 780 950 mv open voltage loop detection threshold measure v(vccl) - v(eaout), relative to error amplifier maximum voltage. 125 300 600 mv open voltage loop detection delay measure phsout pulse numbers from v(eaout) = v(vccl) to pgood = low. 8 pulses over-current comparator input offset voltage 1v v(ocset) 3.3v -30 -13 0 mv ocset bias current r osc = 24.5 k 23.25 24.50 25.75 a over-current delay counter rosc = 7.75 k (phsout=1.5mhz) 4096 cycle over-current delay counter rosc = 15.0 k (phsout=800khz) 2048 cycle over-current delay counter rosc = 50.0 k (phsout=250khz) 1024 cycle over-current limit amplifier input offset voltage -10 0 10 mv transconductance note 1 0.50 1.00 1.75 ma/v sink current 35 55 75 ua unity gain bandwidth note 1 0.75 2.00 3.00 khz downloaded from: http:///
ir3500v page 5 of 34 july 28, 2008 parameter test condition min typ max unit over voltage protection (ovp) comparators threshold at power-up 1.60 1.73 1.83 v threshold during normal operation compare to v(vdac) 110 130 150 mv ovp release voltage during normal operation compare to v(vdac) -13 3 20 mv threshold during dynamic vid down 1.72 1.75 1.77 v dynamic vid detect comparator threshold 25 50 75 mv propagation delay to iin measure time from v(vo) > v(vdac) (250mv overdrive) to v(iin) transition to > 0.9 * v(vccl). 90 180 ns iin pull-up resistance 5 15 propagation delay to ovp measure time from v(vo) > v(vdac) (250mv overdrive) to v(rosc/ovp) transition to >1v. 90 180 ns ovp high voltage measure v(vccl)-v(rosc/ovp) 0 1.2 v ovp power-up high voltage v(vccldrv)=1.8v. measure v(vccl)- v(rosc/ovp) 0 0.2 v vdrp buffer amplifier input offset voltage v(vdrp) ? v(iin), 0.5v v(iin) 3.3v -5 3 11 mv source current 0.5v v(iin) 3.3v 2 30 ma sink current 0.5v v(iin) 3.3v 0.2 0.4 0.6 ma unity gain bandwidth note 1 8 mhz slew rate note 1 4.7 v/ s iin bias current -1 0 1 a pgood output output voltage i(pgood) = 4ma 150 300 mv leakage current v(pgood) = 5.5v 0 10 a under voltage threshold-vo decreasing reference to vdac -380 -330 -280 mv under voltage threshold-vo increasing reference to vdac -315 -265 -215 mv under voltage threshold hysteresis 25 60 95 mv vccl_drv activation threshold i(pg)=4ma, v(pg)<400mv, v(vccl)=0 1 2 3.6 v open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(vo) < [v(vosen+) ? v(lgnd)] / 2 35 60 85 mv vosen+ open sense line comparator threshold compare to v(vccl) 87.5 90.0 92.5 % vosen- open sense line comparator threshold 0.36 0.40 0.44 v sense line detection source currents v(vo) = 100mv 200 500 700 ua downloaded from: http:///
ir3500v page 6 of 34 july 28, 2008 note 1: guaranteed by design, but not tested in production note 2: vdac output is trimmed to compensate for error amp lifier input offset errors vid codes & system set point vid hex vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vset 40 0 0 0 1.220 44 0 0 1 1.195 48 0 1 0 1.170 4c 0 1 1 1.145 50 1 0 0 1.120 54 1 0 1 1.095 58 1 1 0 1.070 5c 0 1 0 1 1 1 0 0 1.045 table 1 ? vr11.1 cpu vtt vid codes vdac ocset vsetpt fb eaout + - + - rosc ivsetpt isource vdac buffer amplifier isink ivdac rocset 1k fast vdac cvdac + - rosc lgnd remote sense amplifier vo rvdac system set point voltage vosns- rosc buffer amplifier 0.6v eaout ir3500 irosc current source generator + - vosen+ vosen- irosc irosc error amplifier iocset figure 2 - system set point test circuit for vr11.1 vtt vid parameter test condition min typ max unit vccl regulator amplifier reference feedback voltage 1.15 1.19 1.23 v vcclfb bias current -1 0 1 ua vccldrv sink current 10 30 ma uvlo start threshold compare to v(vccl) 91 93 99 % uvlo stop threshold compare to v(vccl) 83 87 91 % hysteresis compare to v(vccl) 7 8.25 9.5 % general vccl supply current 3.0 6.5 10.0 ma downloaded from: http:///
ir3500v page 7 of 34 july 28, 2008 pin description pin# pin symbol pin description 1-8 vid7-0 vid0, 1, 5, 7 are grounded. vid6 is pull ed up. vid2~4 are inputs to vid d to a converter. 9 enable enable input. a logic low applied to this pin puts the ic into fault mode. do not float this pin as the logic state will be undefined. 10 vrhot open collector output of the vrhot compara tor which drives low if hotset pin voltage is lower than 1.6v. connect external pull-u p. 11 hotset a resistor divider including thermistor s enses the temperature, which is used for vrhot comparator. 12 vosen- remote sense amplifier input. connect to ground at the load. 13 vosen+ remote sense amplifier input. connect to output at the load. 14 vo remote sense amplifier output. 15 fb inverting input to the error amplifier. 16 eaout output of the error amplifier. 17 vdrp buffered iin signal. connect an external rc network to fb to program converter output impedance. 18 iin average current input from the phase ic(s). this pin is also used to communicate over voltage condition to phase ics. 19 vsetpt error amplifier non-inverting input. conv erter output voltage can be decreased from the vdac voltage with an external resistor connecte d between vdac and this pin (there is an internal sink current at this pin). 20 ocset programs the constant converter output cur rent limit and hiccup over-current thresholds through an external resistor tied to vda c and an internal current source from this pin. over-current protection can be disab led by connecting a resistor from this pin to vdac to program the threshold higher th an the possible signal into the iin pin from the phase ics but no greater than vccl ? 2 v (do not float this pin as improper operation will occur). 21 vdac regulated voltage programmed by the vid inp uts. connect an external rc network to lgnd to program dynamic vid slew rate and provid e compensation for the internal buffer amplifier. 22 ss/del programs converter startup and over curre nt protection delay timing. it is also used to compensate the constant output current loop duri ng soft start. connect an external capacitor to lgnd to program. 23 rosc/ovp connect a resistor to lgnd to program o scillator frequency and ocset, vsetpt and vdac bias currents. oscillator frequency equals switching frequency per phase. the pin voltage is 0.6v during normal operation and higher than 1.6v if over-voltage condition is detected. 24 lgnd local ground for internal circuitry and ic substrate connection. 25 clkout clock output at switching frequency multi plied by phase number. connect to clkin pins of phase ics. 26 phsout phase clock output at switching frequency per phase. connect to phsin pin of the first phase ic. 27 phsin feedback input of phase clock. connect to phsout pin of the last phase ic. 28 vccl output of the voltage regulator, and power input for clock oscillator circuitry. connect a decoupling capacitor to lgnd. 29 vcclfb non-inverting input of the voltage regula tor error amplifier. output voltage of the regulator is programmed by the resistor divider con nected to vccl. downloaded from: http:///
ir3500v page 8 of 34 july 28, 2008 system theory of operation pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 3. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. input voltage is sensed in phase ics and feed-forward control is re alized. the pwm ramp slope will change with the input voltage a nd automatically compensate for changes in the inpu t voltage. the input voltage can change due to variations in t he silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. pwm comparator rdrp1 vsetpt clkin rcs ccs phsin dacin vcc gateh ishare csin+ gatel eain csin- ccomp1 vcch cbst vccl pgnd sw vid6 phsout vid6 clk d q phsin ccomp rfb + - + - + - + - + - clkin rcs cdrp + - ccs +- rdrp + - 3k gnd vout vdac vo dacin vcc phsin vosns- vosns+ lgnd ishare iin vdrp eain gateh csin- csin+ gatel eaout clkout vin fb irosc vid6 remote sense amplifier vcch rcomp cbst clk 2 r 3 d 1 q 4 q 5 vccl gate drive voltage phsout pwm comparator vid6 vid6 vid6 clk d q + - + - + - + - + - 3k vid6 clk 2 r 3 d 1 q 4 q 5 vid6 - + vid6 + + ramp discharge clamp enable body braking comparator rvsetpt pwm latch current sense amplifier share adjust error amplifier reset dominant 1 2 phase ic pgnd - + sw vid6 + + - + ldo amplifier ramp discharge clamp enable body braking comparator vdrp amp vdac ivsetpt clock generator current sense amplifier reset dominant pwm latch share adjust error amplifier error amplifier rfb1 cout control ic cfb 1 2 phsout phase ic figure 3 - pwm block diagram 30 vccldrv output of the vccl regulator error ampli fier to control external transistor. the pin senses 12v power supply through a resistor. 31 pgood open collector output that drives low duri ng startup and under any external fault condition. indicates converter within regulation. c onnect external pull-up. 32 vidsel float this pin for vr11.1 cpu vtt applica tion downloaded from: http:///
ir3500v page 9 of 34 july 28, 2008 frequency and phase timing control the oscillator and system clock frequency is progra mmable from 250khz to 9mhz by an external resistor (rosc). the control ic system clock signal (clkout) is conn ected to clkin of all the phase ics. the phase tim ing of the phase ics is controlled by the daisy chain loop, wh ere control ic phase clock output (phsout) is conne cted to the phase clock input (phsin) of the first phase ic, an d phsout of the first phase ic is connected to phsi n of the second phase ic, etc. and phsout of the last phase ic is connected back to phsin of the control ic. du ring power up, the control ic sends out clock signals fr om both clkout and phsout pins and detects the feed back at phsin pin to determine the phase number and monitor any fault in the daisy chain loop. figure 4 shows the phase timing for a four phase converter. the switching fr equency is programmed by the rosc resistor as shown in figure 5. the clock frequency equals the number of phase t imes the switching frequency. phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 4 - four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving the falling edge of a clock pulse, the p wm latch is set; the pwm ramp voltage begins to increase; the l ow side driver is turned off, and the high side dri ver is then turned on after the non-overlap time. when the pwm ramp voltage exceeds the error amplifier?s output v oltage the pwm latch is reset. this turns off the high side dr iver, then turns on the low side driver after the n on-overlap time, and activates the ramp discharge clamp. the ramp di scharge clamp quickly discharges the pwm ramp capac itor to the output voltage of the share adjust amplifier in the phase ic until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go up to 100% duty cycle in response to a loa d step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range of the pwm comparator results in 100% d uty cycle regardless of the voltage of the pwm ramp . downloaded from: http:///
ir3500v page 10 of 34 july 28, 2008 figure 5 - frequency variation with rosc this arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cyc le as required. it also favors response to a load step de crease which is appropriate given the low output to input voltage ratio of most systems. the inductor current will in crease much more rapidly than decrease in response to load transients. an additional advantage of the architec ture is that differences in ground or input voltage at the phases have no effect on operation since the pwm ramps are referenced to vdac. the error amplifier is a high speed amplifier with 110 db of open loop gain. it is not unity gain stable. figure 6 depicts pwm operating w aveforms under various conditions. phase ic clock pulse vdac eain pwmrmp gatel gateh duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vcc uv, ocp, vid fault) figure 6 - pwm operating waveforms downloaded from: http:///
ir3500v page 11 of 34 july 28, 2008 body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node v oltage is then forced to decrease until conduction of the synchronous rectifier?s body diode occurs. this inc reases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often c omparable to the output voltage, the inductor curre nt slew rate can be increased significantly. this patented metho d is referred to as ?body braking? and is accomplis hed through the ?body braking comparator? located in the phase ic. if the error amplifier?s output voltage drops b elow the output voltage of the share adjust amplifier in the phase ic, this comparator turns off the low side gate dri ver. lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor, as shown in figure 7. the equation of the sensing netw ork is, cs cs l l cs cs l c c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component o f the inductor current. figure 7 - inductor current sensing and current sen se amplifier c o l r l r cs c cs v o current sense amp csout i l v l v cs c downloaded from: http:///
ir3500v page 12 of 34 july 28, 2008 the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch curre nts. the output voltage can be positioned to meet a load lin e based on real time information. except for a sens e resistor in series with the inductor, this is the only sense me thod that can support a single cycle transient resp onse. other methods provide no information during either load i ncrease (low side sensing) or load decrease (high s ide sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of freq uency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all add itional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 7. it s gain is nominally 32.5 and the 3850 ppm/oc increase in indu ctor dcr should be compensated in the voltage loop feedback path. the current sense amplifier can accept positive dif ferential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the con trol ic and other phases through an on-chip 3k resistor connected to the ishare pin. the ishare p ins of all the phases are tied together and the voltage on the share bus repr esents the average current through all the inductor s and is used by the control ic for voltage positioning and curre nt limit protection. the input offset of this ampli fier is calibrated to +/- 1mv in order to reduce the current sense error. the input offset voltage is the primary source of e rror for the current share loop. in order to achiev e very small input offset error and superior current sense accuracy, t he current sense amplifier continuously calibrates itself. this calibration algorithm creates ripple on the ishare bus with a frequency of fsw / 896 in a multiphase a rchitecture. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compar ed with average current at the share bus. if curren t in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output c urrent; if current in a phase is larger than the av erage current, the share adjust amplifier of the phase will pull u p the starting point of the pwm ramp thereby decrea sing its duty cycle and output current. the current share amplifi er is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. ir3500v theory of operation block diagram the block diagram of the ir3500v is shown in figure 8, and specific features are discussed in the foll owing sections. downloaded from: http:///
ir3500v page 13 of 34 july 28, 2008 uv 275mv enable sam ple d elay disable power not ok fault latch1 vid fault fault latch1 3.3v fault latch2 vid fault latch vccl uvlo vccl ov fault ov@operation ov@start vo ov@operation vccl uvlo sample delay 0.6v reset ov@start ov@operation vccl uvlo oc after vrrdy open sense line vbias open daisy chain oc before vrrdy vccl uvlo ov fault ov fault vccl uvlo ss reset ss reset eaout vccl open voltage loop + - + s r q + - + - + - + - 25k 1 2 6 3 4 5 + - + - + - + - s r q + - + - + - 25k s r q 25k + - + - + - + - + - + - + - s r q + - + - + - 25k + - 0.86 + - s r q vid2 s r q + - vidsel vid5 vid3 vid4 vid6 pgood ss/del enable vid7 clkout vid0 vid1 vccl phsin phsout hotset rosc/ovp vccldrv vcclfb vrhot vosen+ vo vdrp lgnd vosen- fb eaout vdac iin ocset vsetpt vccl vccl vid7 vidsel vid5 vid6 vid3 vid4 vid1 vid2 vid7 vid0 vid5 vid6 vid3 vid4 vid1 vid2 vboot vid0 phsin irosc phsout irosc vidsel vidsel ivosen- vidsel vidsel vidsel irosc disable fault irosc phsout clkout amd 5-bit vr11 boot amd 6-bit vr11 noboot vidsel latch dis irosc fas t vd ac vid0 oc 4.0v ss cleared fault latch1 vid input comparators (1/8 shown) delay comparator set dominant error amplifier enable comparator vo 800mv 1.3us blanking 850mv internal vdac digital to analog converter vboot (1.1v) vdac buffer amplifier set dominant vboot latch vidsel comparators 250ns blanking vccl regulator amplifier over voltage comparator vid sample delay comparator vccl output comparator rosc buffer amplifier current source generator 1.19v vrhot comparator 0.6v vdrp amplifier 0.94 isink isource remote sense amplifier oc delay counter reset dominant power ok latch 80mv 120mv 0.2v discharge comparator 1.2v 1.14v intel amd set dominant 3.5k vid fault latch 1.6v 50mv vid fault 1.73v power-up ov comparator ivosen- ivosen+ 200mv float voltage dynamic vid detect comparator vccl*0.9 vccl-1.2v 0.4v soft start clamp isetpt oc limit comparator 1.4v uv cleared fault latch2 set dominant 60mv 130mv 3mv intel 0.6v open daisy chain open sense line detect comparators open sense line amd 1.0v 4.5ua 3.2v oc limit amplifier iocset idchg open sense line detect comparators detection pulse detection pulse 1.08v set dominant ov fault latch 8-pulse delay 1.5v 0.86 1.6v dvid fault latch2 oc delay reset s r q vccldrv ov@start uv vdac under voltage comparator 400k vccldrv 315mv figure 8 ? ir3500v block diagram vid control the vid pins require an external bias voltage and s hould not be floated. the vid input comparators mon itor the vid pins and control the digital-to-analog converter (d ac) whose output is sent to the vdac buffer amplifi er. the output of the buffer amplifier is the vdac pin. the vdac voltage, input offsets of error amplifier and remote sense differential amplifier are post-package trimmed to provide 0.7% system set-point accuracy. the actual vdac voltage does not directly determine the system accu racy, which has a wider tolerance. the ir3500v can accept changes in the vid code whil e operating and vary the dac voltage accordingly. t he slew rate of the voltage at the vdac pin can be adjusted by an external capacitor between vdac pin and lgnd pin. a resistor connected in series with this capacitor is required to compensate the vdac buffer amplifier. digital vid transitions result in a smooth analog transition of the vdac voltage and converter output voltage mini mizing inrush currents in the input and output capacitors and ove rshoot of the output voltage. downloaded from: http:///
ir3500v page 14 of 34 july 28, 2008 adaptive voltage positioning adaptive voltage positioning is implemented needed to reduce the output voltage deviations during load transients and the power dissipation of the load at heavy load . the circuitry related to voltage positioning is s hown in figure 9. the output voltage is set by the reference voltage vsetpt at the positive input to the error amplifier . this reference voltage can be programmed to have a constant dc off set bellow the vdac by connecting rsetpt between vd ac and vsetpt. the ivsetpt is controlled by the rosc a s shown in figure 10. csin- iin csin+ csin- vosen- vdrp ishare phase ic eaout vo phase ic current sense amplifier ishare + - rfb 3k + - 3k rdrp + - + - ... ... vdac vdac remote sense amplifier vsetpt rsetpt vdac ivsetpt fb vdac error amplifier current sense amplifier control ic vdrp amplifier + - csin+ vosen+ figure 9 - adaptive voltage positioning figure 10 - isetpt, ocset with rosc downloaded from: http:///
ir3500v page 15 of 34 july 28, 2008 the voltage at the vdrp pin is a buffered version o f the share bus iin and represents the sum of the d ac voltage and the average inductor current of all the phases. the vdrp pin is connected to the fb pin through th e resistor r drp . since the error amplifier will force the loop to maintain fb to be equal to the vsetpt, an additiona l current will flow into the fb pin equal to (vdrp-vsetpt) / r drp . when the load current increases, the adaptive pos itioning voltage increases accordingly. more current flows t hrough the feedback resistor r fb , and makes the output voltage lower proportional to the load current. the positio ning voltage can be programmed by the resistor r drp so that the droop impedance produces the desired converter outp ut impedance. the offset and slope of the converter output impedance are referenced to and therefore independe nt of the vdac voltage. remote voltage sensing vosen+ and vosen- are used for remote sensing and c onnected directly to the load. the remote sense differential amplifier with high speed, low input o ffset and low input bias current ensures accurate v oltage sensing and fast transient response. inductor dcr temperature compensation a negative temperature coefficient (ntc) thermistor should be used for inductor dcr temperature compen sation. the thermistor should be placed close to the induct or and connected in parallel with the feedback resi stor, as shown in figure 11. the resistor in series with the thermistor is used to reduce the nonlinearity of t he thermistor. eaout + - + - vsetpt iin rsetpt vdac ivsetpt error amplifier vdac control ic vdrp amplifier vdrp rdrp rt rfb1 rfb fb vosen- remote sense amplifier vo + - vosen+ figure 11 - temperature compensation of inductor dc r start-up sequence the ir3500v has a programmable soft-start function to limit the surge current during the converter sta rt-up. a capacitor connected between the ss/del and lgnd pin s controls soft start timing, over-current protecti on delay and hiccup mode timing. a charge current of 52.5ua and discharge current of 4ua control the up slope a nd down slope of the voltage at the ss/del pin respectively . downloaded from: http:///
ir3500v page 16 of 34 july 28, 2008 figure 12 depicts the start-up sequence vr11 vid wi th boot voltage. if there is no fault, the ss/del p in will start charging when the enable crosses the threshold. the error amplifier output eaout is clamped low until ss/del reaches 1.4v. the error amplifier will then regulat e the converter?s output voltage to match the ss/de l voltage less the 1.4v offset until the converter output reaches the 1.1v boot voltage. the ss/del voltage continues to increase until it rises above the 3.0v threshold of vid dela y comparator. the vid set inputs are then activated and vdac pin transitions to the level determined by the vid inpu ts. the ss/del voltage continues to increase until it rises above 3.92v and allows the pgood signal to be asserted. s s/del finally settles at 4.0v, indicating the end o f the soft start. soft start time (td2) td5 vrrdy 3.92v ss/del (12v) start delay (td1) vcc enable 1.4v vout 4.0v vid sample time (td3) vdac normal operation 3v td4 vrrdy delay time (td4+td5) 1.1v vid eaout figure 12 - start-up sequence vccl under voltage lock-out, vid fault modes, over current, as well as a low signal on the enable inpu t immediately sets the fault latch, which causes the eaout pin to drive low turning off the phase ic dri vers. the pgood pin also drives low, and ss/del begin to disc harge until the voltage reaches 0.2v. if the fault has cleared the fault latch will be reset by the discharge comp arator allowing a normal soft start to occur. other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chai n, set different fault latches, which start discharging ss /del, pull down eaout voltage and drive pgood low. however, the latches can only be reset by cycling vccl power . constant over-current control during soft start the over current limit threshold is set by a resist or connected between ocset and vdac. if the iin pin voltage, which is proportional to the average current plus v dac voltage, exceeds the ocset voltage during soft start, the constant over-current control is activated. figure 13 shows the constant over-current control with del ay during soft start. the delay time is set by the rosc resistor, which sets the number of switching cycles for the d elay counter. downloaded from: http:///
ir3500v page 17 of 34 july 28, 2008 the delay is required since over-current conditions can occur as part of normal operation due to inrus h current. if an over-current occurs during soft start (before pgood is asserted), the ss/del voltage is regulated by t he over current amplifier to limit the output current below the threshold set by ocset voltage. if the over-cu rrent condition persists after delay time is reached, the fault lat ch will be set pulling the error amplifier?s output low and inhibiting switching in the phase ics. the ss/del capacitor wi ll discharge until it reaches 0.2v and the fault la tch is reset allowing a normal soft start to occur. if an over-c urrent condition is again encountered during the so ft start cycle, the constant over-current control actions will repeat a nd the converter will be in hiccup mode. the delay time is controlled by a counter which is triggered by clock . the counter values vary with switching frequency per phase in order to have a similar delay time for different sw itching frequencies. over-current protection (output shorted) normal operation 3.88v ea hiccup over-current protection (output shorted) power-down ocp delay start-up with output shorted normal operation 3.92v ss/del iout vout vrrdy 1.1v enable ocp threshold 4.0v normal start-up (output shorted) normal start-up internal oc delay figure 13 - over current protection waveforms durin g and after soft start over-current hiccup protection after soft start the over current limit threshold is set by a resist or connected between ocset and vdac pins. figure 13 shows the constant over-current control with delay after pgood is asserted. the delay is required since over -current conditions can occur as part of normal operation du e to load transients or vid transitions. if the iin pin voltage, which is proportional to th e average current plus vdac voltage, exceeds the oc set voltage after pgood is asserted, it will initiate the disch arge of the capacitor at ss/del. the magnitude of t he discharge current is proportional to the voltage difference b etween iin and ocset and has a maximum nominal valu e of 55ua. if the over-current condition persists long e nough for the ss/del capacitor to discharge below t he 120mv offset of the delay comparator, the fault latch wil l be set pulling the error amplifier?s output low a nd inhibiting switching in the phase ics and de-asserting the pgo od signal. the output current is not controlled dur ing the delay time. the ss/del capacitor will discharge unt il it reaches 200 mv and the fault latch is reset a llowing a normal soft start to occur. if an over-current con dition is again encountered during the soft start c ycle, the over- current action will repeat and the converter will b e in hiccup mode. downloaded from: http:///
ir3500v page 18 of 34 july 28, 2008 linear regulator output (vccl) the ir3500v has a built-in linear regulator control ler, and only an external npn transistor is needed to create a linear regulator. the output voltage of the linear regulator can be programmed between 4.75v and 7.5v by the resistor divider at vcclfb pin. the regulator outpu t powers the gate drivers and other circuits of the phase ics along with circuits in the control ic, and the volt age is usually programmed to optimize the converter efficiency. the linear regulator can be compensated by a 4.7uf capa citor at the vccl pin. due to stability reasons, th ere is an upper limit to the maximum value of capacitor that can be used at this pin and it?s a function of the number of phases used in the multiphase architecture and thei r switching frequency. figure 14 provides bode plot s for the linear regulator with 5 phases switching at 750 khz . figure 14 - vccl regulator stability with 5 phases and phsout equals 750 khz. vccl under voltage lockout (uvlo) the ir3500v has no under voltage lockout for conver ter input voltage (vcc), but monitors the vccl volt age instead, which is used for the gate drivers of phas e ics and circuits in control ic and phase ics. dur ing power up, the fault latch will be reset if vccl is above 94% of the voltage set by resistor divider at vcclfb pi n. if vccl voltage drops below 86% of the set value, the fault latch will be set. vid fault codes vid codes of 0000000x and 1111111x will set the fau lt latch and disable the error amplifier. a 1.3us d elay is provided to prevent a fault condition from occurrin g during dynamic vid changes. a vid fault condition is latched and can only be cleared by cycling power to vccl. voltage regulator ready (pgood) the pgood pin is an open-collector output and shoul d be pulled up to a voltage source through a resist or. during start-up, it is pulled low with an input voltage as low as 2 v. until the soft start cycle is complete , pgood remains low until the output voltage is within regulation a nd ss/del is above 3.92v. the pgood pin drives low if the fault latch, over voltage latch, open sense line latch, o r open daisy chain latch is set. a high level at th e pgood pin indicates that the converter is in operation and ha s no fault. the pgood stays high as long as the out put voltage is within 300 mv of the programmed vid. downloaded from: http:///
ir3500v page 19 of 34 july 28, 2008 open voltage loop detection the output voltage range of error amplifier is dete cted all the time to ensure the voltage loop is in regulation. if any fault condition forces the error amplifier output a bove vccl-1.08v for 8 switching cycles, the fault l atch is set. the fault latch can only be cleared by cycling power to vccl. load current indicator output the vdrp pin voltage represents the average current of the converter plus the vdac voltage. the load c urrent information can be retrieved by a differential ampl ifier that subtracts the vdac voltage from the vdrp voltage. enable input pulling the enable pin below 0.8v sets the fault la tch and a voltage above 0.85v enables the soft star t of the converter. thermal monitoring (vrhot) a resistor divider including a thermistor at the ho tset pin sets the vrhot threshold. the thermistor i s usually placed at the temperature sensitive region of the c onverter, and is linearized by a series resistor. t he ir3500v compares the hotset pin voltage with a reference vo ltage of 1.6v. the vrhot pin is an open-collector o utput and should be pulled up to a voltage source through a resistor. if the thermal trip point is reached t he vrhot output drives low. the hysteresis of the vrhot comp arator is added to eliminate toggling of vrhot outp ut. over voltage protection (ovp) the output over-voltage happens during normal opera tion if a high side mosfet short occurs or if outpu t voltage is out of regulation. the over-voltage protection comp arator monitors the output of the remote sense ampl ifier (vo pin). if the vo pin voltage exceeds vdac by 130mv, as shown in figure 15, the ir3500v raises the rosc/ ovp pin voltage to v(vccl) - 1v. this signal can be used by the host system as an indication that an over volt age event has occurred enabling an appropriate response such as disabling the ac-dc converter. the rosc/ovp pin can also be connected to a thyrister in a crowbar circu it to blow an input fuse. the over voltage condition also sets the over volta ge fault latch, which pulls the error amplifier out put low to turn off the converter output. at the same time the iin pin (ishare of phase ics) is pulled up to vccl to commu nicate the over voltage condition to phase ics, as shown in fi gure 15. in each phase ic, an ovp circuit overrides the normal pwm operation and will fully turn-on the low side mo sfet within approximately 150ns. the low side mosfe t will remain on until the ishare pin voltage drops below v(vccl) - 800mv, which signals the end of over volt age condition. an over voltage fault condition is latch ed in the ir3500v and can only be cleared by cyclin g power to the ir3500v vccl. in the event of a high side mosfet short before pow er up, the ovp flag is activated with as little sup ply voltage as possible, as shown in figure 16. the vosen+ pin is compared against a fixed voltage of 1.73v (typical) for ovp conditions at power-up. the rosc/ovp pin will be p ulled higher than 1.6v with vccldrv voltage as low as 1.8v. an external mosfet or comparator should be used to disable the silver box, activate a crowbar, or turn off the supply source. the 1.8v threshold is used to preven t false over-voltage triggering caused by pre-charg ing of output capacitors. downloaded from: http:///
ir3500v page 20 of 34 july 28, 2008 pre-charging of converter output voltage may trigge r ovp. if the converter output is pre-charged above 1.73v as shown in figure 17, the rosc/ovp pin voltage will b e higher than 1.6v when vccldrv voltage reaches 1.8 v. rosc/ovp pin voltage will be vccldrv-1v and rise wi th vccldrv voltage until vccl is above uvlo thresho ld, after which rosc/ovp pin voltage will be vccl-1v. t he converter cannot start unless the over voltage c ondition stops and vccl is cycled. if the converter output i s pre-charged 130mv above vdac but lower than 1.73v , as shown in figure 18, the converter will soft start u ntil ss/del voltage is above 3.92v (4.0v-0.08v). th en, the over voltage comparator is activated and fault latch is set. during dynamic vid down, ovp could be triggered whe n output voltage can not follow vdac voltage change at light load with large output capacitance. therefore , the over-voltage threshold is raised to 1.73v fro m vdac+130mv whenever dynamic vid is detected and the difference between output voltage and vdac is more than 50mv, as shown in figure 19. the over-voltage threshold is c hanged back to vdac+130mv if the difference is smal ler than 50mv. the overall system must be considered when designin g for ovp. in many cases the over-current protectio n of the ac-dc or dc-dc converter supplying the multiphase c onverter will be triggered and provide effective pr otection without damage as long as all pcb traces and compon ents are sized to handle the worst-case maximum cur rent. if this is not possible, a fuse can be added in the in put supply to the multiphase converter. after ovp 130mv fault latch output voltage (vo) ovp threshold iin (ishare) vccl-800 mv ovp condition normal operation gateh (phase ic) gatel (phase ic) error amplifier output (eaout) vdac figure 15 - over-voltage protection during normal o peration downloaded from: http:///
ir3500v page 21 of 34 july 28, 2008 vccl+0.7v vccl+0.7v 12v rosc/ovp output voltage (vosen+) vccldrv vccl uvlo 1.6v 12v vcc 1.8v figure 16 - over-voltage protection during power-up rosc/ovp output voltage (vosen+) 1.8v 1.6v vccldrv vccl uvlo vcc 12v vccl+0.7v vccl+0.7v 1.73v figure 17 - over-voltage protection with pre-chargi ng converter output vo > 1.73v downloaded from: http:///
ir3500v page 22 of 34 july 28, 2008 vid + 0.13v vccl - 1v ss/del 3.92v (4v-0.08v) rosc/ovp output voltage (vosen+) vccl+0.7v vccl+0.7v 0.6v vccldrv vccl uvlo 1.73v vcc 12v figure 18 - over-voltage protection with pre-chargi ng converter output vid + 0.13v ir3500v page 23 of 34 july 28, 2008 open remote sense line protection if either remote sense line vosen+ or vosen- or bot h are open, the output of remote sense amplifier (v o) drops. the ir3500v monitors vo pin voltage continuously. i f vo voltage is lower than 200 mv, two separate pul se currents are applied to vosen+ and vosen- pins resp ectively to check if the sense lines are open. if v osen+ is open, a voltage higher than 90% of v(vccl) will be present at vosen+ pin and the output of open line d etect comparator will be high. if vosen- is open, a volta ge higher than 700mv will be present at vosen- pin and the output of open-line-detect comparator will be high. the open sense line fault latch is set, which pull s the error amplifier output low immediately and shut down the converter. the ss/del voltage is discharged and the fault latch can only be reset by cycling vccl power. open daisy chain protection ir3500v checks the daisy chain every time it powers up. it starts a daisy chain pulse on the phsout pi n and detects the feedback at phsin pin. if no pulse come s back after 32 clkout pulses, the pulse is restart ed again. if the pulse fails to come back the second time, the o pen daisy chain fault is registered, and ss/del is not allowed to charge. the fault latch can only be reset by cyclin g the power to vccl. after powering up, the ir3500v monitors phsin pin f or a phase input pulse equal or less than the numbe r of phases detected. if phsin pulse does not return wit hin the number of phases in the converter, another pulse is started on phsout pin. if the second started phsout pulse does not return on phsin, an open daisy chai n fault is registered. phase number determination after a daisy chain pulse is started, the ir3500v c hecks the timing of the input pulse at phsin pin to determine the phase number. this information is used to have symm etrical phase delay between phase switching without the need of any external component. single phase operation in an architecture where only a single phase is nee ded the switching frequency is determined by the cl ock frequency. fault operation table the fault table shown in figure 20 describes the di fferent faults that can occur and how ir3500v will react to protect the supply and the load from possible damag e. the fault types that can occur are listed in row 1. row 2 has the method that a fault is cleared. the first 5 fau lts are latched in the uv fault latch and the vccl power has to be recycled by switching off the input and switching i t back on for the converter to work again. the rest of the faults (except for uvlo vout) are latched in the ss fault latch and do not require the vccl power to be recyc led in order to resume normal operation once the fault condition clears. most of the faults disable the error ampli fier (ea) and discharge the soft start capacitor. all the faults flag pgood. pgood returns back to high when the fau lts are cleared. the delay row shows reaction time after de tecting a fault condition. delays are provided to m inimize the possibility of nuisance faults. downloaded from: http:///
ir3500v page 24 of 34 july 28, 2008 fault type open daisy open control loop open sense line over voltage vid disable vccl uvlo oc before start-up oc after start-up vout uvlo fault clearing method recycle vccl resume normal operation when condition clears error amp disabled yes no rosc/ovp & iin drive high until ov clears no yes no ss/del discharge yes no flags pgood yes delay? 32 clock pulses 8 phsout pulses no no 1.3us blank time 250 ns blank time no phsout pulses. count programmed by rosc value ss/del discharge threshold no figure 20 ? fault table applications information design procedure oscillator resistor rosc the oscillator of ir500 generates square-wave pulse s to synchronize the phase ics. the switching frequ ency of each phase converter equals the phsout frequency, w hich is set by the external resistor r osc according to the curve in figure 23. the clkout frequency equals the switching frequency multiplied by the phase number . the rosc sets the reference current used for the no loa d offset and ocset which is given by figure 5 and e quals: rosc iocset isetpt 595 .0 = = (1) soft start capacitor c ss/del the soft start capacitor c ss/del programs five different time parameters. they incl ude soft start delay time, soft start time, vid sample delay time, vr ready delay t ime and over-current fault latch delay time after v r ready. the ss/del pin voltage controls the slew rate of th e converter output voltage, as shown in figure 12. after the enable pin voltage rises above 0.85v, there is a so ft-start delay time td1 , after which the error amplifier output is released to allow the soft start of output volta ge. the soft start time td2 represents the time dur ing which converter voltage rises from zero to 1.1v . the vid sample delay time (td3) is the time period when vid stays at boot voltage of 1.1v. vid rise or fall time (td4) i s the time when vid changes from boot voltage to th e final voltage. the vr ready delay time (td5) is the time period from vr reaching the final voltage to the vr ready signal being issued, which is determined by the del ay comparator threshold. c ss/del = 0.1uf meets all the specifications of td1 to td5 , which are determined by (2) to (6) respectively. 6 / / 10*5.52 4.1* 4.1* 1 ? = = del ss chg del ss c i c td (2) downloaded from: http:///
ir3500v page 25 of 34 july 28, 2008 6 / / 10*5.52 1.1* 1.1* 2 ? = = del ss chg del ss c i c td (3) 6 / / 10 *5.52 7.0* )1.1 4.1 3(* 3 ? = ? ? = del ss chg del ss c i c td (4) 6 / / 10*5.52 1.1 * 1.1 * 4 ? ? = ? = dac del ss chg dac del ss v c i v c td (5) 4 10 *5.52 92.0* 4 )3 92.3(* 5 6 / / td c td i c td del ss chg del ss ? = ? ? = ? (6) the minimum over-current fault latch delay time t ocdel is determined by the value of c ss/del and can be quantified as 6 / / 10 * 55 12.0* 12.0* ? = = del ss dischg del ss ocdel c i c t (7) vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac down-slope sr down can be programmed by the external capacitor c vdac as defined in (8), where i sink is the sink current of vdac pin. the slew rate of v dac up-slope is the same as that of down- slope. down down sink vdac sr sr i c 6 10*44 ? = = (8) the resistor r vdac is used to compensate vdac circuit and can be calc ulated as follows 2 15 10 2.3 5.0 vdac vdac c r ? ? + = (9) over current setting resistor r ocset the inductor dc resistance is utilized to sense the inductor current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm/c, and therefo re the maximum inductor dcr can be calculated from (10), where r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t_ room respectively. )] ( 10* 3850 1[ _ 6 _ _ room max l room l max l t t r r ? ? + ? = ? (10) the total input offset voltage (v cs_tofst ) of current sense amplifier in phase ics is the su m of input offset (v cs_ofst) of the amplifier itself and that created by the am plifier input bias current flowing through the curr ent sense resistor r cs . cs csin ofst cs tofst cs r i v v ? + = + _ _ (11) the over-current limit is set by the external resis tor r ocset and is given by (12). in a multiphase architecture the peak to peak ripple of the net inductor current is much smaller than the stand alone phase due to inte rleaving. the ratio of the peak to average current in this ca se can be approximated using (13). downloaded from: http:///
ir3500v page 26 of 34 july 28, 2008 ocset cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1( [ _ _ ? + + ? ? = (12) ( ) ) 1( 2 / ) 1 () ( ) 1( d d fl n i d n m n m d n d d v k sw limit i p ? ??? ?? ? + ? ? ?? ? ?? = (13) where; i limit =over current limit, n=number of phases, k p =ratio of the peak to average current for the induc tor, g cs =gain of the current sense amplifier, i ocset = determined by the rosc and given by figure 10, d=vo/v i , m=maximum integer that doesn?t exceed (n*d) no load output voltage setting resistor r vsetpt , a resistor between vsetpt pin and vdac is used to c reate output voltage offset v o_nlofst, which is the difference between v dac voltage and output voltage at no load condition. r vsetpt is determined by (14), where i vsetpt is the current flowing out of vsetpt pin as shown i n figure 23. vsetpt nlofst o vsetpt i v r _ = (14) vccl capacitor c vccl the capacitor is selected based on the stability r equirement of the linear regulator and the load cur rent to be driven. the linear regulator supplies the bias and gate drive current of the phase ics. a 4.7uf normal ly ensures stable vccl performance. vccl programming resistor r vcclfb1 and r vcclfb2 since vccl voltage is proportional to the mosfet ga te driver loss and inversely proportional to the mosfet conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. vcc l linear regulator consists of an external npn transi stor, a ceramic capacitor and a programmable resist or divider. pre-select r vcclfb1 , and calculate r vcclfb2 from (15). 19.1 19.1* 1 2 ? = vccl r r vcclfb vcclfb (15) vccl regulator drive resistor r vccldrv the drive resistor is primarily dependent on the l oad current requirement of the linear regulator and the minimum input voltage requirements. the following e quation gives an estimate of the average load curre nt of the switching phase ics. [ ] n ma f q q i sw gt gb avg drive ? + ? + = 10 ) ( _ (16) q gb and q gt are the gate charge of the top and bottom fet. for a minimum input voltage and a maximum vccl, the maximum r vccldrv required to use the full pull-down current of the vccl driver is given by min _ / (max) 7.0 (min) avg drive i vccldrv i vccl v r ? ? = (17) due to limited pull down capability of the vccldrv pin, make sure the following condition is satisfied . downloaded from: http:///
ir3500v page 27 of 34 july 28, 2008 ma r vccl v vccldrv i 10 (min) 7.0 (max) < ? ? (18) in the above equation, v i ( min) and v i ( max) is the minimum and maximum anticipated input voltage. if the above condition is not satisfied there is a need to use a device with higher min or darlington configuration can be used instead of a single npn transistor. thermistor r therm and over temperature setting resistors r hotset1 and r hotset2 the threshold voltage of vrhot comparator is fixed at 1.6v, and a negative temperature coefficient (nt c) thermistor r therm is required to sense the temperature of the power stage. if we pre-select r therm , the ntc thermistor resistance at allowed maximum temperatur e t max is calculated from (19). )] 1 1 (* [ * _ _ room max l therm therm tmax t t b exp r r ? = (19) select the series resistor r hotset2 to linearize the ntc thermistor, which has non-line ar characteristics in the operational temperature range. then calculate r hotset1 corresponding to the allowed maximum temperature tmax from (20). 6 . 1 )6.1 (*) ( 2 1 ? + = vccl r r r hotset tmax hotset (20) voltage loop compensation the adaptive voltage positioning (avp) is usually a dopted in the computer applications to improve the transient response and reduce the power loss at heavy load. l ike current mode control, the adaptive voltage posi tioning loop introduces an extra zero to the voltage loop a nd splits the double poles of the power stage, whic h makes the voltage loop compensation much easier. adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. pre-select feedback resistor r fb, and calculate the droop resistor rdrp, o cs max l fb drp r n g r r r ? ? = * _ (21) the selection of compensation types depends on the output capacitors used in the converter. for applic ations using electrolytic, polymer or al-polymer capacitor s and running at lower frequency, type ii compensat ion shown in figure 21(a) is usually enough. while for the ap plications using only ceramic capacitors and runnin g at higher frequency, type iii compensation shown in figure 21 (b) is preferred. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 21 - voltage loop compensation network downloaded from: http:///
ir3500v page 28 of 34 july 28, 2008 for applications where avp is not required, the com pensation is the same as for the regular voltage mo de control. for converters using polymer, al-polymer, and ceramic capacitors, which have much higher esr zero frequency, type iii compensation is required as sho wn in figure 22(b) with r drp and c drp removed. type ii compensation for avp applications determine the compensation at no load, the worst ca se condition. choose the crossover frequency fc bet ween 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capaci tor across the output inductors matches that of the inductor, and determine r cp and c cp from (23) and (23), where l e and c e are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. 2 2 ) * * * 2( 1 * 5 ) 2( c c i fb e e c cp r c f v r c l f r + ? ? ? ? ? = (22) cp e e cp r c l c ? ? = 10 (23) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough. type iii compensation for avp applications determine the compensation at no load, the worst ca se condition. assume the time constant of the resis tor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by (24) and (25), where r le is the equivalent resistance of inductor dcr. le fb cs e drp c r r g c r f ? ? = * * 2 1 (24) 180 )5.0 tan( 90 1 ? ? = a c (25) choose the desired crossover frequency fc around fc 1 estimated by (24) or choose fc between 1/10 and 1 /5 of the switching frequency per phase, and select the c omponents to ensure the slope of close loop gain is -20db per decade around the crossover frequency. choose r esistor r fb1 according to (26), and determine c fb and c drp from (27) and (28). fb fb r r 2 1 1 = to fb fb r r 3 2 1 = (26) 1 4 1 fb c fb r f c ? ? = (27) drp fb fb fb drp r c r r c ? + = ) ( 1 (28) r cp and c cp have limited effect on the crossover frequency, an d are used only to fine tune the crossover frequency and transient load response. determine r cp and c cp from (29) and (30). i fb e e c cp v r c l f r 5 ) 2( 2 ? ? ? ? ? = (29) downloaded from: http:///
ir3500v page 29 of 34 july 28, 2008 cp e e cp r c l c ? ? = 10 (30) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough. type iii compensation for non-avp applications resistor r drp and capacitor c drp are not needed. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the de sired phase margin c. calculate k factor from (31), and determine the component values based on (32) to (36 ), )]5.1 180 ( 4 tan[ + ? = c k (31) k v f c l r r i c e e fb cp ? ? ? ? ? ? = 5 ) 2( 2 (32) cp c cp r f k c ? ? = 2 (33) cp c cp r k f c ? ? ? = 2 1 1 (34) fb c fb r f k c ? ? = 2 (35) fb c fb c k f r ? ? ? = 2 1 1 (36) downloaded from: http:///
ir3500v page 30 of 34 july 28, 2008 pcb layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to t he ic. dedicate at least one middle layer for a ground pl ane lgnd. connect the ground tab under the control ic to lgn d plane through a via. place vccl decoupling capacitor vccl as close as p ossible to vccl and lgnd pins. place the following critical components on the sam e layer as control ic and position them as close as possible to the respective pins, r osc , r ocset , r vdac , c vdac , and c ss/del . avoid using any via for the connection. place the compensation components on the same laye r as control ic and position them as close as possi ble to eaout, fb, vo and vdrp pins. avoid using any via fo r the connection. use kelvin connections for the remote voltage sens e signals, vosns+ and vosns-, and avoid crossing ov er the fast transition nodes, i.e. switching nodes, ga te drive signals and bootstrap nodes. avoid analog control bus signals, vdac, iin, and e specially eaout, crossing over the fast transition nodes. separate digital bus, clkout, phsout and phsin fro m the analog control bus and other compensation components. vid5 vosns - fb eaout rosc / ovp to vin r hotset1 vdac ocset vsetpt iin to system lgnd plane clkout phsout vcclfb vidsel vrrdy vdrp vid4 vid3 vid2 vid0 ss/del r fb r vccldrv c ss/del c vdac r drp c cp to voltage remote sense vid1 vid6 vid7 vccldrv vccl phsin enable lgnd c vccl to lgnd vrhot hotset vosns+ vo r hotset2 r fb1 c fb1 r cp c cp1 c drp to phase ics r vdac r osc/ovp to phase ics to vccl to thermistor r vccl1 r vccl2 to ovp circuit r fb2 to thermi stor vid5 vosns - fb eaout rosc / ovp to vin r hotset1 vdac ocset vsetpt iin to system lgnd plane clkout phsout vcclfb vidsel vrrdy vdrp vid4 vid3 vid2 vid0 ss/del r fb r vccldrv c ss/del c vdac r drp c cp to v oltage remote sense vid1 vid6 vid7 vccldrv vccl phsin enable lgnd c vccl to lgnd vrhot hotset vosns+ vo r hotset2 r fb1 c fb1 r cp c cp1 c drp to phase ics r vdac r osc/ovp to phase ics to vccl to thermistor r vccl1 r vccl2 to ovp circuit r fb2 to thermistor downloaded from: http:///
ir3500v page 31 of 34 july 28, 2008 pcb metal and component placement lead land width should be equal to nominal part lea d width. the minimum lead to lead spacing should b e 0.2mm to minimize shorting. lead land length should be equal to maximum part le ad length + 0.3 mm outboard extension + 0.05mm inbo ard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extensi on will accommodate any part misalignment and ensure a fill et. center pad land length and width should be equal to maximum part pad length and width. however, the m inimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) four 0.3mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to m inimize the noise effect on the ic and to transfer heat to the pcb. no pcb traces should be routed nor vias placed unde r any of the 4 corners of the ic package. doing so can cause the ic to rise up from the pcb resulting in poor so lder joints to the ic leads. downloaded from: http:///
ir3500v page 32 of 34 july 28, 2008 solder resist the solder resist should be pulled away from the me tal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is reco mmended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm w ill always ensure nsmd pads. the minimum solder resist width is 0.13mm. at the inside corner of the solder resist where the lead land groups meet, it is recommended to provid e a fillet so a solder resist width of 0.17mm remains. the land pad should be solder mask defined (smd), w ith a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignmen t. in 0.5mm pitch cases it is allowable to have th e solder resist opening for the land pad to be smaller than the part pad. ensure that the solder resist in-between the lead l ands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands f rom the pad land. the four vias in the land pad should be tented or p lugged from bottom board side with solder resist. downloaded from: http:///
ir3500v page 33 of 34 july 28, 2008 stencil design the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. r educing the amount of solder deposited will minimize the occurr ence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lea d land. the land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float an d the lead lands will be open. the maximum length and width of the land pad stenci l aperture should be equal to the solder resist ope ning minus an annular 0.2mm pull back to decrease the incidenc e of shorting the center land to the lead lands whe n the part is pushed into the solder paste. downloaded from: http:///
ir3500v page 34 of 34 july 28, 2008 package information 32l mlpq (5 x 5 mm body) ? ja = 24.4 o c/w, jc =0.86 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on ir?s web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on . www.irf.com www.irf.com downloaded from: http:///

▲Up To Search▲

Price & Availability of IR3500VMPBF

	To Download IR3500VMPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .